|
Dr. Shugang Wei
Professor
Department of Computer Science, Gunma University. Wei＠gunma-u.ac.jp |
Education
Research Interests
Publications
Experience
Membership
|
Education:
Doctor of Engineering in
Electronic Engineering, Tohoku University, Sendai, Japan, March 1990.
Research area majored in algorithms and architectures of VLSI systems, digital
signal processing with VLSI, parallel processing for arithmetic and
multiple-valued integrated circuits.
Dissertation:" Studies of Encryption Processor Based on the Multiple-Valued
Integrated Circuits".
M.S. in Computer Science,
Gunma University, Kiryu, Japan, March 1987.
Researched on design and test of logic circuit networks.
Developed a CAD system for logic circuit networks with
PASCAL.
Thesis: " Studies of Synthesis of Multilevel Feed-Forward Logic Networks".
B.S. in Radio Engineering,
Harbin Institute of Technology, Harbin, China,July 1982.
Research
Interests:
Current research interests
are in the areas of high-speed arithmetic circuits, ASIC and FPGA design for
digital signal processing and controlling, and embedded computing systems.
Publications
(Proceedings of International Conferences and Journals):
C.
Jiang and S. Wei,
Residue-Weighted Number Conversion Using Signed-Digit Number for Moduli Set {22n-1, 22n+1+1, 2n},
Analog Integrated Circuits and Signal
Processing, Vol. ?, no.?, pp.?-?, ( 2013).
M. Zhang and S. Wei,
High-Speed Modular multipliers Based on a New Binary Signed-Digit Adder Tree Structure,
Journal of Circuits, Systems, and Computers, Vol. 22, no.6, pp.1350043(18 pages) (DOI: 10.1142/S0218126613500436)
(June 2013)
M.
Zhang and S. Wei,
New Binary Modular Adder Tree Structure for Arithmetic
of Error Checker of Arithmetic,
Journal of
Communication and Computer, Vol. 10, No.3, pp.295-300, (March 2013).
C.
Jiang and S. Wei,
Residue-Weighted Number Conversion for Moduli Set {2n-1, 2n+1, 22n+1,
2n} Using Signed-Digit Number,
Journal of Circuits, Systems, and Computers, Vol. 22, no.1, pp.1250070(17 pages) (DOI: 10.1142/S0218126612500703) (Jan. 2013)
S. Wei,
Residue-Binary Number Conversion Using Signed-Digit Arithmetic for a Three-Moduli Set,
IEEE Proceedings of TENCON2012, pp.371-374, Cebu, Philippines (Nov. 2012).
S. Wei,
An RSA encryption Implementation Method Using Signed-Digit Arithmetic Circuits,
IEEE Proceedings of 5th
International Conference on Biomedical Engineering and Informatics, pp.1337-1341, Chongqing, China (Oct. 2012).
S. Wei and C. Jiang,
Residue Signed-Digit Arithmetic and the Conversion
between Residue and Binary Numbers for a Four-Moduli
Set,
Proceedings of 11th International Symposium on Distributed Computing and
Applications to Business, Engineering and Science, pp. 436-440, Guilin, China (Oct. 2012)
S. Wei,
Sequential Modular Multipliers Using Residue
Signed-Digit Additions,
Journal of
Communication and Computer, Vol. 9, No.8, pp.872-878, (Aug. 2012).
C.
Jiang and S. Wei,
Residue-Weighted Number Conversion for Moduli Set {22n-1, 22n+1+1, 2n}
Using Signed-Digit
Number,
Proceedings of the 10th Annual IEEE Northeast Workshop on Circuits and Systems,
pp.9-12, Montreal, Canada
(June 2012).
S. Wei,
A Sequential Modular Multiplication Algorithm Using
Signed-Digit Additions,
IEEE Proceedings of TENCON2011, pp.370-374, Bali, Indonesia (Nov. 2011).
M.
Zhang and S. Wei,
Efficient Residue Checker Using New Binary Modular
Adder Tree Structure for Arithmetic of Error Detection,
Proceedings of Eighth International Conference on Fuzzy Systems and Knowledge
Discovery, pp. 2481-2485, Shanghai, China (July 2011)
M.
Zhang and S. Wei,
High-Speed Modular
multipliers Based on a New Binary Signed-Digit Adder
Tree Structure,
Proceedings of Ninth International Symposium on Distributed Computing and
Applications to Business, Engineering and Science, pp. 615-619, Hong Kong, China (Aug. 2010)
C.
Jiang and S. Wei,
Residue-Weighted Number Conversion with Moduli Set {2p-1, 2p+1, 22p+1,
2p} Using Signed-Digit Number Arithmetic,
Proceedings of Ninth International Symposium on Distributed Computing and
Applications to Business, Engineering and Science, pp. 629-633, Hong Kong, China (Aug. 2010)
S. Wei,
Modular multipliers Using a Modified Residue Addition Algorithm with
Signed-Digit Number Representation,
Lecture Notes in Engineering and Computer Science, International MultiConference of Engineers and Computer Scientists 2009,
Vol. 1, pp.494-499, Hong Kong (March 2009).
S. Wei and Wenhai Xu,
FPGA implementation of gain calculation using a polynomial expression for audio
signal level dynamic compression,
J.Acoust. Soc. Jpn.(E), Vol.29, No.6, pp.372-377(2008)
S. Wei,
A New Residue Adder with Redundant Binary Number Representation,
Proceedings of the 6th Annual IEEE Northeast Workshop on Circuits and Systems,
pp.157-160, Montreal, Canada (June 2008).
S. Wei,
A Multiplicative Inverse Algorithm Based on Modulo 2p-1 Signed-Digit Arithmetic for Residue to Weighted Number
Conversion,
Proceedings of 2007 IEEE International Symposium on Integrated Circuits pp.25-28, Singapore (Sept. 2007)
S. Wei and Wenhai Xu,
Acoustic Level Dynamic Compression Characteristics with FPGA Implementation,
Proceedings of the 7th International Conference on Signal, Speech and Image
Processing,
pp.8-13, Beijing, China (Sept. 2007)
S. Chen and S. Wei,
A Fast Algorithm for RNS-to-Binary Conversion,
WSEAS Transactions on Computers, Issue 5, Vol. 6, pp.733-740 (May 2007)
S. Wei,
A Binary Floating-Point Adder with the Signed-Digit Number Arithmetic,
WSEAS Transactions on Computer Research, Issue 1 , Vol. 2, pp.61-65 (Jan, 2007)
S. Chen and S. Wei,
A High-Speed Realization of Chinese Remainder Theorem,
Proceedings of the 2007 WSEAS International Conference on Circuits, Systems,
Signal and Telecommunications, pp.1-6, Queensland, Australia (Jan. 2007)
S. Wei,
Binary Floating-Point Adder with the Signed-Digit Number Representations,
Proceedings of the 2007 WSEAS International Conference on Computer Engineering and
Applications, pp. 528-532, Quenslang, Australia (Jan.
2007)
S. Chen and S. Wei,
Performance Evaluation of Signed-Digit Architecture for Weighted-to-Residue and
Residue-to-Weighted Number Converters with Moduli Set (2n-1, 2n, 2n +1),
IPSJ Journal, Vol. 47, no. 6, pp.1884-1893 (2006)
S. Chen and S. Wei,
Weighted-to-Residue and Residue-to-Weighted Converters with Three-Moduli (2n-1, 2n +1) Signed-Digit Architectures,
Proceedings of the 2006 IEEE Symposium on Circuits and Systems, vol.? pp.3365-3368, Kos, Greece(May 2006)
S. Wei and K. Shimizu,
Modulo $(2^{p} \pm 1)$ Multipliers Using a Three-Operand Modular Signed-Digit
Addition Algorithm,
Journal of Circuits, Systems, and Computers, Vol. 15, no.1, pp.129-144 (Feb.
2006)
S. Chen and S. Wei,
New Booth Modulo $m$ Multipliers with Signed-Digit Number Arithmetic,
IPSJ Journal, Vol. 46, no. 12, pp.3030-3039 (Dec. 2005)
S. Wei,
Number Conversions between RNS and Mixed-Radix Number System Based on Modulo (2p-1) Signed-Digit
Arithmetic,
ACM proceedings of the 2005 Symposium on Integrated Circuits and Systems Design, pp.160-165,
Brazil (Sept. 2005).
R. Kawamata
and S. Wei,
Square-Rooting Algorithm Using Signed-Digit Arithmetic,
Proceedings of the 2005 International Technical Conference on Circuits/Systems,
Computers and Communications, Vol.2 pp.559-600, Korea (July 2005)
S. Wei and K. Shimizu,
Dynamic Range Compression Characteristics Using an Interpolation Polynomial for
Digital Audio Systems,
IEICE TRANS. FUNDAMENTALS, Vol. E88-A, No.2, pp.586-589(Feb. 2005)
S. Wei and K. Shimizu,
A New RNS to Mixed-Radix Number Converter Using Modulo 2p-1 Signed-Digit Arithmetic,
Proceedings of 2004 IEEE Asia Pacific Conference On Circuits and Systems,
vol.1, pp.377-380, Tainan, Taiwan.(Dec. 2004)
S. Chen, S. Wei and K.
Shimizu,
Booth Memoryless Modular Multiplier with Signed-Digit
Number Representation,
Proceedings of 2004 IEEE Asia Pacific Conference On Circuits and Systems,
vol.1, pp.21-24, Tainan, Taiwan.(Dec. 2004)
S. Wei and T. Mutoh,
FPGA Design of Audio Signal Level Compressor,
Proceedings of the 2004 International Technical Conference on Circuits/Systems,
Computers and Communications, 7C1L-3 pp.1-4, Sendai, Japan (July 2004)
S. Wei and K. Shimizu,
Audio Dynamic Range Compression Characteristics Based on an Interpolation Polynomial,
Proceedings of the 2nd Annual IEEE Northeast Workshop on Circuits and Systems,
pp.133-136, Montreal, Canada (June 2004)
S. Wei and K. Shimizu,
Modulo $(2^{p} \pm 1)$ Multipliers Using a Three-Operand Modular Addition and
Booth Recoding Based on Signed-Digit Number Arithmetic,
Proceedings of the 2003 IEEE Symposium on Circuits and Systems, vol.V, pp.221-224, Bangkok, Thailand(May 2003)
S. Chen, S. Wei and K.
Shimizu,
Modular Multipliers Based on a Modified Booth Recoding Method with Signed-Digit
Number Representation,
Proceedings of the 2002 International Technical Conference on Circuits/Systems,
Computers and Communications, Vol.1 pp.559-564, Kang-Won Do, Korea (July 2003)
S. Wei and K. Shimizu,
Residue Checker with Signed-Digit Arithmetic for Error Detection of Arithmetic
Circuits,
Journal of Circuits, Systems, and Computers, Vol. 12, no. 1, pp.41-53 (Jan.
2003)
S. Wei, S. Chen and K.
Shimizu,
Fast Modular Multiplication Using Booth Recoding Based on Signed-Digit Number
Arithmetic,
Proceedings of 2002 IEEE Asia Pacific Conference On Circuits and Systems,
vol.2, pp.31-36, Bali, Indonesia.(Oct. 2002)
S. Wei and K. Shimizu,
Residue Signed-Digit Arithmetic Circuit with a Complement of Modulus and the
Application to RSA Encryption Processor,
Proceedings of the 9th IEEE International Conference on Electronics, Circuits
and Systems, Vol.2, pp.591 - 594, Dubrovnik, Croatia (Sept. 2002)
S. Chen, S. Wei and K.
Shimizu,
A Booth Recording Method for Serial Modular Multipliers with Signed-Digit
Number Representation,
Proceedings of the 2002 International Conference on Fundamentals of
Electronics, Communications and Computer Siences,
pp.II.10-15, Tokyo, Japan (March 2002)
S. Wei and K. Shimizu,
Error Detection of Arithmetic Circuits Using a Residue Checker with
Signed-Digit Number System,
Proceedings of the 2001 IEEE International Symposium on Defect and Fault
Tolerance in VLSI Systems, pp.72-77, San Francisco, USA (Oct. 2001)
S. Wei and K. Shimizu,
Parallel Modular Arithmetic Based on Signed-Digit Number System and the
Application to Error Detection of Product-Sum Computation,
Proceedings of the 2001 International Symposium on Distributed Computing and
Applications to Business, Engineering and Science, pp. 19-23, Wuhan, China(Oct.
2001)
S. Wei and K. Shimizu,
Fast Residue Arithmetic Multipliers Based on a Signed-Digit Number System,
Proceedings of the 8th IEEE International Conference on Electronics, Circuits
and Systems, Vol.1, pp.263 - 266, Malta (Sept. 2001)
S. Wei, M. Zhang and K.
Shimizu,
A VLSI Implementation Method of a Compressor for Audio Systems,
J.Acoust. Soc. Jpn.(E), Vol.22, No.6, pp.407-414(June 2001)
S. Wei, M. Zhang and K.
Shimizu,
Dynamic Acoustic Signal Processing,
Proceedings of 2000 World Multiconference on Systemics, Cybernetics and Informatics, Vol.VI, pp.288-293,
Orlando, Florida, USA (July 2000)
S. Wei and K. Shimizu,
Residue Arithmetic Circuits Using a Signed-Digit Number Representation,
Proceedings of the IEEE 2000 International Symposium on Circuits and Systems,
Vol.-I, pp.24-27, Geneva, Switzerland (May 2000)
S. Wei and K. Shimizu,
Residue Arithmetic with a Signed-Digit Number System,
Proceedings of 4th International Conference/Exhibition on High-Performance
Computing in Asia-Pacific Region, pp.349-354, Beijing, China (May 2000)
S. Wei and K. Shimizu,
A Novel Residue Arithmetic Hardware Algorithm Using a Signed-Digit Number
Representation,
IEICE TRANS. INF. & SYST., Vol. E83-D, No.12, pp.2056-2064(Dec. 2000)
S. Wei and K. Shimizu,
Compact Residue Arithmetic Multiplier Based on the Radix-4 Signed-Digit
Multiple-Valued Arithmetic Circuits,
IEICE TRANS. ELECTRONICS, Vol. E82-C, No.9, pp.1647-1654(Sept. 1999)
S. Wei and K. Shimizu,
Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the
VHDL Implementation,
Proceedings of Ninth Great Lakes Symposium on VLSI, pp.218-221, Ann Arbor,
Michigan, USA (March 1999)
S. Wei and K. Shimizu,
Residue Arithmetic Multiplier Based on the Radix-4 Signed-Digit Multiple-Valued
Arithmetic Circuits,
Proceedings of 12th International Conference on VLSI Design, pp. 212-217, Goa,
India (Jan. 1999)
S. Wei and K. Shimizu,
Residue Arithmetic Circuits Based on the Signed-Digit Multiple-Valued
Arithmetic Circuits,
IEEE Proceedings of 28th International Symposium on Multiple-Valued Logic,
pp.276-281, Fukuoka, Japan (May 1998)
S. Wei, M. Zhang and K.
Shimizu,
Realization of Over-easy Characteristic of Compressor/limiter on a Digital Signal
Processor,
J.Acoust. Soc. Jpn.(E), Vol.18, No.2, pp.59-66(Feb. 1997)
S. Wei and K. Shimizu,
Modulo 2p-1 Arithmetic Hardware Algorithm Using Signed-Digit Number
Representation,
IEICE TRANS INF.& SYST., Vol. E79-D,No.3, pp.242-246 (March 1996)
S. Wei, K. Shimizu and M.
Zhang,
Realization of Dynamic Range Controllers on a Digital Signal Processor for
Audio Systems,
J.Acoust. Soc. Jpn.(E), Vol.16, No.6, pp.353-362 (Nov. 1995)
S. Wei and K. Shimizu,
Design of Digital Signal Level Meters for Audio Systems Based on the State
Transitions,
J.Acoust. Soc. Jpn.(J), 51(4), pp.291-298(April 1995)(in Japanese)
S. Wei and N. Seki,
Design of compressor/limiter on a digital signal processor,
J.Acoust. Soc. Jpn.(J), 50(4), 263-270(April 1994)(in Japanese)
S. Wei,K.
Shimizu and M. Zhang,
Design of an ASIC for Digital Audio Signal Level Meters,
IEEE Proceedings of Seventh Annual IEEE International ASIC Conference and
Exhibit, pp.288-291, Rochester, USA (Sept. 1994)
Read this paper.
S.
Wei, M. Kameyama and T. Higuchi,
Performance Evaluation of a Multiple-Valued RSA Encryption VLSI,
Trans.IEICE. Japan, Vol. J73-D-I, No. 5, pp. 484-491
(May 1990)(in Japanese).
(The English translation appeared in :" Systems and Computers in
Japan", Vol. 22, No. 7, pp. 12-21, Scripta Technica Inc., USA, 1991)
M.
Kameyama, S. Wei and T. Higuchi,
Design of an RSA Encryption Processor Based on the Signed-Digit Multiple-Valued
Arithmetic Circuits,
Trans.IEICE. Japan, Vol. J71-D, No. 12, pp. 2659-2668
(Dec. 1988)(in Japanese).
(The English translation appeared in :" Systems and Computers in
Japan", Vol. 21, No. 6, pp. 21-31, Scripta Technica Inc., USA, 1990)
S.
Wei and K. Shimizu,
Synthesis of Multilevel Feed-Forward NOR Networks,
Trans.IEICE. Japan, Vol. J70-D, No. 2, pp. 325-334
(Feb. 1987)(in Japanese)
K.
Shimizu and S. Wei,
Synthesis of Multilevel Feed-Forward NAND Networks,
Trans. IEICE. Japan, Vol. J69-E, No. 7, pp. 785-787 (July 1986)
Publications(Book):
S. Wei,
Introduction to Information and Systems (Book Chapter 3 : Computer Structure ),
Tokyo Book Press(1996)(in Japanese).
Main
Experience:
March
2007 - Present
Professor, Department of Production and Technology, Gunma University, Kiryu, Japan.
October 2006 – March 2007
Professor, Department of Computer Science, Gunma University, Kiryu, Japan.
January 1997 - September
2006
Associate Professor, Department of Computer Science, Gunma University, Kiryu, Japan.
April 1993 -
December 1996
Assistant Professor, Department of Computer Science, Gunma University, Kiryu, Japan.
April 1990 - March 1993
Engineer in Audio-Video Systems Division, Matsushita Communication Industrial Co.,Ltd., Yokohama, Japan.
Performed design and development of multi-processors and ICs
for professional audio systems. Created and programmed the algorithms
for digital signal processing with DSPs. Developed the simulation and modeling
systems on MS-DOS and UNIX with Assembly, C, and Fortran.
Performed scheduling, coding, layout, debugging, testing, and
documentation of product designs, and failure analysis for custom services.
Major products completed:
PANASONIC RAMSA WZ-DM30 and PANASONIC RAMSA WZ-DE40 ( digital multi-processors
for professional audio systems, sold worldwide). An ASIC IC for acoustic signal
controlling was designed.
August 1982 -
October 1984
Assistant Professor, Department of Radio Engineering, Harbin Institute of
Technology, Harbin, China.
Membership:
The Institute of Electronics,
Information and Communication Engineers(IEICE) of
Japan.
The Acoustical
Society of Japan.
The Institute of Electrical
and Electronics Engineers(IEEE).
Conference and Reviewer's activities for publications:
Session Chairman, 2007 IEEE
International Symposium on Integrated Circuits(ISIC2007)
Session Chairman, 7th
International Conference on Signal, Speech and Image Processing(SSIP07)
IEEJ Trans. EIS
Integration, the VLSI Journal
IEE Proc. Computers &
Digital Techniques
The 2007 IEEE International
Symposium on Circuits and Systems (ISCAS2007)
The 36th IEEE International
Symposium on Multiple-Valued Logic (ISMVL2006)
The 2004 IEEE International
Midwest Symposium on Circuits and Systems (MWSCAS 2004)
The 3rd International
Symposium on Communications and Information Technologies (ISICT2003)
The 2003 IEEE International
Symposium on Circuits and Systems (ISCAS2003)
29th IEEE International
Symposium on Multiple-Valued Logic(1999)
Journal of Circuits, Systems,
and Computers (JCSC)
IEICE TRANS.J-D-1, IEICE
TRANS.E-D, IEICE TRANS.E-A
IEEE TRANS. on Circuits and
Systems: Part II
IEEE TRANS. on Computers
Member of VLSI design (VLD)
research technical committee of IEICE(2001 - 2007)
Associate Editor of Special
Issue on VLSI Design and CAD Algorithms,
IEICE Trans. Vol.E85-A,No.12(2002),
Vol.E86-A,No.12(2003), Vol.E87-A,No.12(2004), and Vol.E88-A,No.12(2005)
Technical Program Committee
Member of 2002 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS
2002)